The present invention relates to an apparatus and a method for manufacturing a semiconductor device having a wiring structure between inter-layer insulating films. The present invention also relates to an apparatus and a method for manufacturing a semiconductor device having a multilayer wiring structure on a substrate where transistors are formed.
Due to downsizing of wiring sizes, the wiring resistance and wiring capacitance tend to steadily increase and have come to greatly affect the operation frequency and power consumption of the devices. Hence, to reduce the wiring capacitance and to realize higher performance of the device, studies and developments have been eagerly made with respect to an SiO2 film (FSG), an organic SiO2 film, an organic film, and the like added with F having a low dielectric constant, in place of an SiO2 film (Pxe2x80x94SiO2 film) formed by a plasma CVD method which has been conventionally used as an inter-layer insulating film.
Any of those materials, however, has advantages and disadvantages compared with the Pxe2x80x94SiO2 film, so that various problems exist in application of those materials to inter-layer insulating films in an LSI.
A problem concerning an FSG film is reduction of moisture absorption caused when F is added at a high concentration (the dielectric constant decreases in proportion to the addition amount of F) and is left in the atmosphere. Where this moisture absorption is considered, it is known that the practical application range of the FSG film is 3.3 or more.
Meanwhile, the organic SiO2 film has an excellent moisture-absorption resistance even in case of a material having a low dielectric constant of 3.0 or less. However, there is a problem that it is not possible to perform processing of a fine hole pattern which causes cracking due to an O2 plasma used for peeling a resist. Taking into consideration these problems, it has been difficult to adopt an organic SiO2 film of a single layer film as an inter-layer insulating film in an LSI.
Therefore, discussion is made as to application of a combination of an organic SiO2 film and, for example, an inorganic film of SiN, SiO2, FSG, or the like to an inter-layer insulating film in a multilayer wiring. However, the dielectric constant is higher compared with the case of using an organic SiO2 film as a single layer. In addition, in case where organic SiO2 films are multilayered into four or five layers, there is a problem that cracking is caused in heating steps or peeling occurs in CMP steps. As a result, it has been difficult to prepare a multilayer wiring which provides high reliability by the combination of an organic film and an inorganic film.
The above problems will be explained with reference to the drawings.
FIG. 1 is a cross-sectional view showing a semiconductor device which realizes a multilayer structure by combining a silicon oxide film and an FSG film. The reference 81 denotes a Pxe2x80x94SiO2 film and the references 84, 88, 92, 96, and 100 are respectively first to fifth Al wirings. FSG films are used for 85, 89, 93, and 97 as inter-layer films. Also, the references 82, 86, 90, 94, and 98 are inter-wiring films, i.e., films which insulate wirings in one same wiring layer from each other and organic silicon oxide films having a predetermined carbon concentration are used for the inter-wiring films. Also, Nb films are used for the references 83, 87, 91, 95, and 99 as liner materials. In this multilayer structure, cracking 101 occurs due to a stress in the organic silicon oxide film as a inter-wiring film of the Al wiring 84 which is in the lowermost layer.
FIG. 2 shows a single wiring structure, and the reference 111 is an organic silicon oxide film having a BPSG film on which devices not shown are formed, and the references 112 and 113 are organic silicon oxide films having a predetermined carbon concentration. In case of manufacturing this wiring structure, an anti-reflection film (ARL) and a resist are applied and developed when patterning an organic silicon oxide film 113. RIE is used to process a groove. However, if RIE using an O2 gas is used to remove the anti-reflection and resist, cracking 114 occurs at the bottom portion of the groove.
FIG. 3 is an enlarged view of a main part of a wiring structure, like FIG. 2. The reference 121 denotes a Pxe2x80x94SiO2 film, and the reference 122 denotes an organic silicon oxide film having a predetermined carbon concentration. An Al wiring 124 is formed in a groove portion formed in the organic silicon oxide film 122, with an Nb film 123 as a liner material interposed. On the Al wiring 124 and the organic silicon oxide film 122, an organic silicon oxide film 125 having a predetermined carbon concentration is formed as an inter-layer film. Also, to make contact with Al wiring 124, a hole from which the Al wiring 124 is exposed is formed in the organic silicon oxide film 125.
If etching is performed during formation of this hole, etching sufficiently reaches the bottom surface in case of forming a hole 126 having relatively loose dimensions. Otherwise, in case of forming a hole 127 having a fine small hole 127, a polymerized product contained in the organic silicon oxide film 126 is created. If this polymerized product is created, there appears a phenomenon of etch-stop in which the resist merely shifts back and stops halfway, resulting in a problem that the etching cannot sufficiently reaches the Al wiring 124.
Thus, in case of a conventional wiring structure, cracking occurs in an inter-layer insulating film in a heating step and during peeling of a resist. A problem hence appears in that the etch-stop occurs during formation of a wiring groove.
Meanwhile, in a multilayer wiring of a large scale integrated circuit (LSI), the following problem has been cited. An upper-layer wiring is constructed under looser rules than a lower-layer wiring, and the width and thickness of the upper-layer wiring are two to four times larger than those of the lower-layer wiring. For example, the uppermost-layer wiring of a logic device having a gate length of 0.25 xcexcm has a wiring width and a wiring thickness which respectively reach 2.2 xcexcm and 1.6 xcexcm. This wiring has a seven times larger compared with the first-layer wiring, as well as a three times larger thickness. This is to restrict the RC delays of the signal wirings as much as possible. The resistance component is decreased by increasing the cross-sectional area of the wiring, and the inter-wiring capacitance component and the inter-layer distance capacitance component are decreased by increasing the inter-wiring distance and the inter-layer distance. In this case, since the size in the thickness direction is increased, the film thickness must be increased with respect to an insulating film (hereinafter called an inter-layer insulating film) corresponding to the portion of the wiring layers on the structure.
However, even an insulating film made of one single layer cannot be deposited as thick as possible. Problems appearing when an insulating film is deposited to be thick will be explained with reference to FIG. 4. The semiconductor device shown in FIG. 4 is a semiconductor device which has a wiring structure of n layers. inter-wiring insulating films 2, 6, 14, and 17 and inter-layer insulating films 4, 8, 10, and 14 are alternately formed on a semiconductor substrate 1. Further, a first-layer wiring 3, a second-layer wiring 7, an (nxe2x88x921)-th-layer wiring layer, and an n-th-layer are consecutively formed between the insulating films, thereby forming a wiring structure of n layers. In this semiconductor device, it has been found that both the wiring width and thickness of the (nxe2x88x921)-th-layer wiring 13 and the n-th-layer wiring 18 are larger than the first-layer-wiring 3 and the second-layer-wiring 7.
However, if the film thickness of the (nxe2x88x921)-th-layer wiring 13 and that of the n-th-layer wiring 18 reach a certain critical film thickness, it is generally known that cracks 12a to 12c, 17a, and 17b are created or peeling (17c) is caused due to a stress which the insulating film 12 or 17 formed between the wirings 13 or 18 have. The problems of cracking and peeling still remain even if Damascene wiring is adopted.
In particular, when using an organic insulating film in which a dangling bond of a film forming element is ended by a methyl group or an ethyl group and a low-dielectric-constant film such as a silica-based porous film which has a micron physical space in the film or a concentration difference, the problems appear more clearly. At this time, the critical film thickness is about 1 xcexcm. This critical film thickness is disclosed as a xe2x80x9cULSI flattened organic coating film materialxe2x80x9d in xe2x80x9cElectric Materialsxe2x80x9d August, p. 53 (1996) by Masao Otake et. al. In the future, this critical film thickness will surely make a significant obstacle in manufacturing a device using a low-dielectric-constant insulating film.
Thus, in semiconductor devices using conventional multilayer wiring structures, delays of signals are restricted, and it is therefore considered that the inter-wiring distance and inter-layer distance need to be large. To realize this, the dimension in the wiring thickness direction must be increased thereby increasing the dimensions of the insulating films formed between the wirings. However, there is a risk of cracking or peeling due to the critical film thickness of the insulating film itself.
An object of the present invention is to provide a semiconductor device having a multilayer wiring structure with high reliability and a manufacturing method thereof.
Another object of the present invention is to provide a semiconductor device having a reduced influence of stress and a manufacturing method thereof.
According to an aspect of the present invention, there is provided a semiconductor device having a wiring structure in which at least one wiring layer including a wiring and an insulating film surrounding the wiring is formed on a substrate, wherein the insulating film of the at least one wiring layer has a carbon concentration and a metal oxide concentration, at least one of which differs in a film thickness direction.
According to another aspect of the present invention, there is provided a semiconductor device having a multilayer wiring structure in which a plurality of wiring layers each including a wiring and an insulating film surrounding the wiring are formed and layered on a substrate, wherein the insulating film of at least one of the plurality of wiring layers has a carbon concentration and a metal oxide concentration, at least one of which is different from a carbon concentration and a metal oxide concentration of the insulating film of another one of the plurality of wiring layers.
Also, according to another aspect of the present invention, there is provided a semiconductor device comprising: a wiring layer including a first insulating film and a plurality of wirings formed with the first insulating film interposed therebetween; a pillar formed by forming a metal film on the wiring layer and by removing selectively the metal film, thereby to make contact with the wiring; a second insulating film formed on the wiring layer so as to cover a side portion of the pillar; a third insulating film formed on the second insulating film and having a carbon concentration higher than that of the second insulating film; and a groove portion formed by removing selectively the third insulating film so as to expose the pillar.
Also, according to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising steps of: forming a metal film on a wiring layer including a plurality of wirings formed with a first insulating film interposed therebetween; forming a pillar in contact with the wirings by removing selectively the metal film such that the wiring layer is exposed; forming a second insulating film on the wiring layer so as to cover a side portion of the pillar; forming a third insulating film having a carbon concentration higher than that of the second insulating film, on the second insulating film; and forming a groove portion to be connected with the wirings, in the third insulating film.
Also, according to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising steps of: forming a second insulating film and a third insulating film having a carbon concentration and a metal oxide concentration, at least one of which differs from a carbon concentration and a metal oxide concentration of the second insulating film, on a wiring layer including a plurality of wirings formed with a first insulating film interposed therebetween; forming selectively a hole portion in the second and third insulating films; and forming a groove portion in the third insulating film so as to overlap the hole portion, with the second insulating film used as a stopper.
In the present invention, in the wiring structure formed on the substrate, the carbon concentration or the metal oxide concentration.is made different with respect to the insulating film at least one of a wiring layer. As a result, etch-stop which is caused when performing fine hole processing on the insulating film can be prevented. Also, if etching is used when forming a wiring groove in the insulating film, occurrence of cracking caused at the bottom surface when peeling a resist can also be prevented.
In particular, pillar process is used for making a contact which connects wirings with each other. As a result, fine hole processing is not necessary any more, so inter-layer insulating films and inter-wiring insulating films can be formed of materials having a low-dielectric constant. In addition, when forming a wiring groove above the pillar, the carbon concentration or the metal oxide concentration of the insulating film formed between pillars in one same layer is made different from the insulating film formed thereon. As a result of this, the controllability of the groove depth in processing of a wiring groove to be formed in the insulating film is improved so that the resistance variants of the wirings due to the groove depth can be restricted.
Also, according to the other aspect of the present invention, the carbon concentration or metal oxide concentration is made different between the layers of each other. As a result of this, the mechanical strength of the multiplayer wiring can be improved so that occurrence of cracking can be prevented.
Thus, according to the present invention, the reliability of the wiring structure can be improved.
Also, according to another aspect of the present invention, there is provided a semiconductor device having a multilayer wiring structure in which a plurality of wiring layers formed with an inter-wiring insulating film interposed therebetween are formed on a substrate with an inter-layer insulating film interposed therebetween, wherein the inter-wiring insulating film in at least one of the wiring layers corrects a stress caused in a film width direction in directions in which the stress is relaxed or at least one of a film stress and a film hardness value of the inter-wiring insulating film differs in a film thickness direction so that cracking might not be caused.
A definition will now be made with reference to an example of a stress "sgr"f which is caused when a thin film made of SiO2 is formed on a Si substrate.
"sgr"f=Es/6(1xe2x88x92xcexd)xc2x7ds2/(dfxc2x7a)xe2x80x83xe2x80x83(1)
The stress can be expressed as above. In this expression, xcexd is a Poisson ratio of the Si substrate, Es is a Young""s modulus, ds is the thickness of the Si substrate, a is a radius of curvature, and df is the thickness of a thin film.
In the expression (1), xcexd and Es are values inherent to materials, and ds and df are defined uniformly. Therefore, the stress "sgr"f is calculated if the radius of curvature a is known.
As shown in FIG. 16, where warp of the Si substrate 161 is h and the diameter of the substrate is D, relationships of a2=r2+(D/2)2 and a=r+h are given. Accordingly, a≈D2/8h is obtained in consideration of D greater than  greater than h. This is substituted in the expression (1), and the following approximation is obtained.
"sgr"f=Es/6(1xe2x88x92xcexd)xc2x7(8h/D2)xc2x7(ds2/df)
From this expression, it can be known that the stress "sgr"f is obtained if the warp h can be measured.
Also, the film hardness is micro Vickers hardness Hv. Generally, the film hardness is defined as Hv=(2Fxc2x7sin136xc2x0/2)/d2 in a fine hardness test using a Vickers indenter of an equilateral rectangular pyramid having a face angle of 136xc2x0.
The structure of an inter-wiring insulating film which corrects the stress caused in the film width direction in which the stress is relaxed includes the following case. For example, if there is a layered structure comprised of a plurality of insulating films, the structure includes a case where one insulating film is made of a material which relaxes the stress of another insulating film, not only in case where adjacent layers are made of materials whose film stresses act in directions opposite to each other but also in case where the film stresses act in one same direction.
To achieve the object described above, according to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising steps of: forming an insulating film having a film stress or a film hardness value which differs in a film thickness direction; forming a groove at a predetermined position of the insulating film; forming and burying a conductive film, including the groove; and removing the conductive film formed at portions other than the groove, thereby to form a wiring for connecting the substrate with the insulating film.
In the present invention, in a semiconductor device having a multilayer wiring structure, an insulating film having a structure in which at least one of the film stress and the film hardness differs in the film thickness direction is used as an inter-wiring insulating film formed between wirings, and correction is made in a direction in which the stress caused in the film width direction is relaxed. Accordingly, it is possible to prepare a multilayer wiring structure which does not cause cracking or peeling in the inter-wiring insulating film.
In addition, by applying the inter-wiring insulating film having this structure to the uppermost wiring layer or the two uppermost wiring layers, it is possible to suppress effectively cracking and peeling caused at the wiring layer portions where the film thickness and the film width are particularly large.
Also, as an inter-wiring insulating film of this kind, an insulating film having high film hardness is formed in contact with an insulating film having a so-called low-dielectric constant, which has a relative dielectric constant of 3 or less. Therefore, not only the problem of the film stress is solved but also reduction of the wiring capacity can be realized.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.